1. Field
The present invention relates to shared virtual memory management, and more particularly, to a shared virtual memory management apparatus for ensuring cache coherence.
2. Description of the Related Art
U.S. Pat. No. 5,592,625 (Jan. 7, 1997) discloses shared virtual memory management based on a memory address translation by use of an adapter card equipped with an input/output buffer, a page table and a control/state register translating all addresses, memory mapping, and packet generation.
A software shared virtual memory uses paging of the shared memory. When an application accesses a certain page for the first time, a page fault is generated, and a page fault handler allocates the page to the application using page fault information.
The software shared virtual memory modifies the page fault handler to ensure data consistency between a plurality of processors at a page level.
Cache coherence protocols are employed to provide data coherence in a hardware manner. Since the cache coherence protocols are built into most existing multicore chips, programmers can easily program using a shared memory programming model. However, an increase in the number of cores may cause a problem of scalability, and thus there may be a need for a substitution method.
When the number of cores increase, the existing methods for ensuring cache coherence have a limitation in improving the overall system performance due to an increase in number of communications. Therefore, a method for ensuring cache coherence using the software shared virtual memory is suggested to provide data consistency in an environment that does not support cache coherence.